
`timescale 1ns / 1ps

`define ZERO_WORD           64'h00000000_00000000
`define REG_BUS             63 :0

`define PC_START            64'h00000000_80000000 
// `define PC_START            32'h3000_0000

`define RAM_ADDR_WIDTH      64
// `define RAM_ADDR_WIDTH      32

`define RAM_DATA_WIDTH      64

`define IRAM_DATA_WIDTH     64
// `define IRAM_DATA_WIDTH     32

`define INST_WIDTH          32
`define DATA_WIDTH          64

`define AXI_ADDR_WIDTH      64
// `define AXI_ADDR_WIDTH      32
`define AXI_DATA_WIDTH      64
`define AXI_ID_WIDTH        4
`define AXI_USER_WIDTH      1

`define SIZE_B              2'b00
`define SIZE_H              2'b01
`define SIZE_W              2'b10
`define SIZE_D              2'b11

`define REQ_READ            1'b0
`define REQ_WRITE           1'b1

`define RISCV_PRIV_MODE_U   0
`define RISCV_PRIV_MODE_S   1
`define RISCV_PRIV_MODE_M   3

`define ALU_SEL_BUS         3:0
`define ALU_SEL_WIDTH       4

`define ALU_SEL_OR          4'b0001
`define ALU_SEL_AND         4'b0010
`define ALU_SEL_XOR         4'b0011
`define ALU_SEL_SLL         4'b0100
`define ALU_SEL_SRL         4'b0101
`define ALU_SEL_SRA         4'b0110
`define ALU_SEL_SLT         4'b0111
`define ALU_SEL_ADD         4'b1000
`define ALU_SEL_SUB         4'b1001

`define TRANSFER_SEL_BUS    2:0
`define TRANSFER_SEL_WIDTH  3

`define TRANSFER_JAL        3'b000
`define TRANSFER_JALR       3'b001
`define TRANSFER_BEQ        3'b010
`define TRANSFER_BNE        3'b011
`define TRANSFER_BLT        3'b100
`define TRANSFER_BGE        3'b101
`define TRANSFER_BLTU       3'b110
`define TRANSFER_BGEU       3'b111

`define MEM_SEL_BUS         3:0
`define MEM_SEL_WIDTH       4

`define MEM_LB              4'b0000
`define MEM_LH              4'b0001
`define MEM_LW              4'b0010
`define MEM_LD              4'b0011
`define MEM_LBU             4'b0100
`define MEM_LHU             4'b0101
`define MEM_LWU             4'b0110
`define MEM_SB              4'b1000
`define MEM_SH              4'b1001
`define MEM_SW              4'b1010
`define MEM_SD              4'b1011

`define CSR_SEL_BUS         1:0
`define CSR_SEL_WIDTH       2

`define CSR_CSRRW           2'b01
`define CSR_CSRRS           2'b10
`define CSR_CSRRC           2'b11

`define RD_SEL_BUS          1:0
`define RD_SEL_WIDTH        2

`define RD_SEL_ALU          2'b00
`define RD_SEL_LINK         2'b01
`define RD_SEL_CSR          2'b10
`define RD_SEL_LOAD         2'b11

`define CSR_MCYCLE          12'hb00
`define CSR_MSTATUS         12'h300
`define CSR_MTVEC           12'h305
`define CSR_MEPC            12'h341
`define CSR_MCAUSE          12'h342
`define CSR_MIE             12'h304
`define CSR_MIP             12'h344
`define CSR_MSCRATCH        12'h340

